1. Field of the Invention
The present invention relates to digital computation circuits and, more particularly, to an integer execution unit having one fewer write port for use with a high-speed microprocessor.
2. Art Background
The heart of any computer or microprocessor is the processor itself. One primary function of any processor is its ability to perform arithmetical or logical operations on various inputs to the processor. The inputs to the processor may include instructions, integers, or addresses. Various schemes are known in the prior art to provide such arithmetic and/or logical operation efficiently. Throughout the development of processors, the emphasis has constantly been placed on increasing the speed of the operation of the processor and components within such processors. Another approach has been directed towards reducing the complexity of the instructions. Yet another approach has been to reduce the actual number of components such as transistors on the processor itself.
Because many mathematical or logical operations performed by a processor involve iterative computation by the integer execution unit, the more recent processors implement a number of simultaneous parallel operations in order to decrease the actual iterative cycle. These simultaneous parallel operations are often referred to as instruction pipeline stages. For example, in one prior art scheme, in carrying out addition operations of two binary numbers, the integer execution units provide for a pair of read ports and a pair of write ports, thus permitting the simultaneous reading and writing of the addition instruction. In a different scheme, the more recent processors utilize the parallel operation technique. The integer execution unit provides for 5 read ports and 8 write ports.
It is to be appreciated that any time savings which can be obtained in any of the arithmetic or logical operations performed by the integer execution unit, will ultimately result in a decrease in the over-all computation time for a given processor. Having multiple read and write ports in the integer execution units allows the simultaneous parallel operations in order to decrease the actual iterative cycle. However, the large number of transistors required to implement a multiple read and write port in the integer execution unit contributes to the complexity of the processor. Accordingly, any decrease in the time required to perform the arithmetic or logical operations by the integer execution unit without requiring the addition of extra write ports in a processor will improve the over-all speed of the processor.